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The AS3643 supports the I C bus protocol. A device that sends data onto the bus is defined as a transmitter and a
the I C bus. Within the bus specifications a standard mode (100kHz maximum clock rate) and a fast mode (400kHz
AS3643
Datasheet, Confidential - D e t a i l e d D e s c r i p t i o n
I 2 C Serial Data Bus
2
device receiving data as a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls the
bus access, and generates the START and STOP conditions must control the bus. The AS3643 operates as a slave on
2
maximum clock rate) are defined. The AS3643 works in both modes. Connections to the bus are made through the
open-drain I/O lines SDA and SCL.
The following bus protocol has been defined ( Figure 27 ):
?? Data
transfer may be initiated only when the bus is not busy.
?? During
data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy
Both data and clock lines remain HIGH.
Start Data Transfer
A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.
Stop Data Transfer
A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.
Data Valid
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of
the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal.
There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes
transferred between START and STOP conditions are not limited, and are determined by the master device. The
information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The
master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold
times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to
enable the master to generate the STOP condition.
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